In computing, the term “cache coherence” generally refers to the consistency of data stored in local caches of a shared resource, such as a main or system memory. Often when processors in a system maintain caches of a common memory resource, problems may arise with inconsistent data. This is often true of processors in a multiprocessing system. In a shared memory multiprocessor system with a separate cache memory for each processor, it is possible to have many copies of any one piece of data. For example, there may be one copy of the data in the main memory and one in each processor's cache memory. When one copy of the data is changed, the other copies of the data may be changed also. Cache coherence is the discipline that ensures that changes in the values of shared data are propagated throughout the system in a timely fashion.
In modern systems, a common problem is how to resolve coherence conflict ordering. For example, if two processors are attempting to access a piece of data, but one wishes to write the data and the other wants to read the data, the timing of the two actions determines what data is read. Often protocol-level methods of ordering are commonly implemented. Generally, to avoid deadlocks, interconnects normally implement a number of “virtual networks” or “virtual channels” for carrying different traffic classes (e.g., requests, snoops, responses, etc.) that must move independently to maintain.
Generally, a memory access or cache transaction involves three messages between the various devices, a request, a response, and an acknowledgment that the response was received. The acknowledgment message (ACK) generally informs the system that the cache transaction has completed and a second cache transaction to the same memory location (e.g., piece of data, etc.) may progress without cache coherency problems. However, these ACKs often result in a large number of small messages consuming system resources and time.